The VPU assembly language is designed to be parallel-friendly while still allowing precise control of the systolic array and its data paths.

Cycle Structure

• Each cycle in the assembly program is marked with $.
• Instructions within the same cycle (before the next $) will be executed in parallel.
• This enables high throughput — for example, loading data and shifting the systolic array simultaneously.
• Some instructions (like WAO) are exclusive and must occupy their own cycle.

LDL — Load Left Buffer

Usage:

• LDLi addr, imm8 — load immediate value into Left buffer at addr
• LDL addr, mem_addr — load from memory into Left buffer

Description:

Loads data into the Left input buffer of the systolic array.

Can be done in parallel with other instructions (except WAO).

LDT — Load Top Buffer

Usage:

• LDTi addr, imm8 — load immediate value into Top buffer at addr
• LDT addr, mem_addr — load from memory into Top buffer

Description:

Loads data into the Top input buffer of the systolic array.