Testbench 1 (Load Instructions, bits 31:30)

Memory is not instantiated, due to which data_in_left and data_in_top are unknown values.

Instructions:

instr_mem[0] = 32'h8000_0001; // Example instruction
instr_mem[1] = 32'h4000_0002;
instr_mem[2] = 32'hC000_0003;
instr_mem[3] = 32'h8000_FF30;

Testbench Display Text

Cycle 0: PC=1, CURR=00000000, NEXT=80000001, STATE=1
Cycle 1: PC=2, CURR=80000001, NEXT=40000002, STATE=2
Cycle 2: PC=3, CURR=40000002, NEXT=c0000003, STATE=3
Cycle 3: PC=3, CURR=40000002, NEXT=c0000003, STATE=2
Cycle 4: PC=4, CURR=c0000003, NEXT=8000ff30, STATE=3
Cycle 5: PC=4, CURR=c0000003, NEXT=8000ff30, STATE=2
Cycle 6: PC=5, CURR=8000ff30, NEXT=80000000, STATE=3
Cycle 7: PC=5, CURR=8000ff30, NEXT=80000000, STATE=2
Cycle 8: PC=6, CURR=80000000, NEXT=80000000, STATE=2
Cycle 9: PC=7, CURR=80000000, NEXT=80000000, STATE=3

Testbench 2 (Swap, Shift and Load Accumulator Instructions, bits 29:25)

Instructions:

// Load Left/Top
instr_mem[0] = 32'h8000_0001; 
instr_mem[1] = 32'h4000_0002;
instr_mem[2] = 32'hC000_0003;
instr_mem[3] = 32'h8000_2F30;

// Swap, shift, and load acc
// Swap
instr_mem[4] = 32'h2000_0001; 
instr_mem[5] = 32'h1000_0002;
instr_mem[6] = 32'h3000_0003;
instr_mem[7] = 32'h3000_0003;

// Shift
instr_mem[8] = 32'h0800_2F30;
instr_mem[9] = 32'h0400_0001;
instr_mem[10] = 32'h0C00_0001;

// Reset
instr_mem[11] = 32'h4000_0002;
instr_mem[12] = 32'hC000_0003;
instr_mem[13] = 32'h8000_2F30;

// Acc Load
instr_mem[14] = 32'h0002_0001;  // Clear Acc
instr_mem[15] = 32'h0001_0001;  // Clear Systolic Array
instr_mem[16] = 32'h0000_8001;  // Clear Left Buffer
instr_mem[17] = 32'h0000_4001;  // Clear Top Buffer

Testbench 3 (Clear Flags, bits 17:14)

Instructions:

// Load Left/Top
instr_mem[0] = 32'h8000_0001; 
instr_mem[1] = 32'h4000_0002;
instr_mem[2] = 32'hC000_0003;
instr_mem[3] = 32'h8000_FF30;

// Swap, shift, and load acc
// Swap
instr_mem[4] = 32'h2000_0001; 
instr_mem[5] = 32'h1000_0002;
instr_mem[6] = 32'h3000_0003;
instr_mem[7] = 32'h3000_0003;

// Shift
instr_mem[8] = 32'h0800_FF30;
instr_mem[9] = 32'h0400_0001;
instr_mem[10] = 32'h0C00_0001;

// Acc Load
instr_mem[11] = 32'h0200_0001;

Testbench 4 (Write Acc to Mem, bit 24)

Instructions:

// Load Left/Top
instr_mem[0] = 32'h8000_0001; 
instr_mem[1] = 32'h4000_0002;
instr_mem[2] = 32'hC000_0003;
instr_mem[3] = 32'h8000_2F30;

// Reset
instr_mem[4] = 32'h0002_0001;  // Clear Acc
instr_mem[5] = 32'h0001_0001;  // Clear Systolic Array
instr_mem[6] = 32'h0000_8001;  // Clear Left Buffer
instr_mem[7] = 32'h0000_4001;  // Clear Top Buffer

// Swap, shift, and load acc
// Swap
instr_mem[8] = 32'h2000_0001; 
instr_mem[9] = 32'h1000_0002;
instr_mem[10] = 32'h3000_0003;
instr_mem[11] = 32'h3000_0003;

// Shift
instr_mem[12] = 32'h0800_2F30;
instr_mem[13] = 32'h0400_0001;
instr_mem[14] = 32'h0C00_0001;

// Accumulator Load
instr_mem[15] = 32'h4200_0002;
instr_mem[16] = 32'hC200_0003;
instr_mem[17] = 32'h8200_2F30;

// Memory Accumulator Output
instr_mem[18] = 32'h0100_0100;  // Get Accumulator Output

Testbench 5 (Write Acc to Mem w/ initialized memory, bit 24)